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PRELIMINARY
KB9223 / KB9223-L
OVERVIEW The KB9223 is a 1-chip BICMOS integrated circuit to perform the function of RF amp and servo signal processor for compact disc player applications.It consist of blocks for RF signal processing ,focus, tracking, sled and spindle servo.Also this IC has adjustment free function and embedded opamp for audio post filter.
RF AMP & SERVO SIGNAL PROCESSOR
80-QFP-1420C
FEATURES * RF amplifier & RF equalizer * Focus error amplifier & servo control * Tracking error amplifier & servo control * Mirror & defect detector circuit * Focus OK detector circuit ORDERING INFORMATION Device KB9223 KB9223-L Package 80-QFP-1420C Tempe. Range -20C ~ +70C
* APC(Auto Laser Power Control) circuit for constant laser APPLICATIONS power * FE bias & focus servo offset adjustment free * EF balance & tracking error gain adjustment free * Embedded audio post filter * The circuit for Interruption countermeasure * Double speed play available * Operating voltage range KB9223 : 5V KB9223-L : 3.4V RELATED PRODUCT * KS9286 Data Processor * KS9284 Data Processor * KA9258D/KA9259D Motor Driver * CD Player * Video-CD
M/M-97-P006 1997. 10. 17
1
PRELIMINARY
KB9223 / KB9223-L
BLOCK DIAGRAM
RF AMP & SERVO SIGNAL PROCESSOR
MDATA
TRCNT
RESET
WDCH
ISTAT
LOCK
ATSC
FGD
MCK
MLT
59
54
22
30
29
31
38
37
36
35
51
52
TZC
58
26
28
27
3
RF-
73
FRSH
FE1
TE1
FE2
FLB
FS3
RF Amp
RFO
74
Micom Data Interface Logic
Focus Phase Compensation
& Offset cancel circuit
60 47 48 57 49
FDFCT FEFEO
PD1 PD2 FEBIAS F E EI
65 66 63 67 68 79
Focus Error Amp
FE-BIAS Adjustment
TDFCT
TETEO TE2 LPFT
Tracking Error Amp E/F Balance & Gain Control MICOM TO SERVO CONTROL AUTO SEQUENCER
Tracking Phase Compensation Block & Jump Pulse GEN.
50 53 55 62 61 43
TG2 TGU SLO SLSL+
PD
69
APC Amp
LD
LDON
70
ADJUSTMENT-FREE CONTROL
VR
Sled Servo Amplifier & Sled Kick GEN.
44 42 46
71
Center Voltage Amp. RF Level AGC & Equalizer
EQC EQO IRF
78 76 75
SPDLO SPDLSMDP SMON
FS1~ FS4
TM1~ BAL1~ PS1~ TM6 BAL5 PS4
GA1~ GA5
Spindle Servo LPF ( Double Speed )
45 23 24
ASY EFM RFI
32 33 77
EFM Comparator
Mirror Detection Circuit FOK Detection Circuit
15
GC1O
25 6 39 1
SMEF FSET
MIRROR MCP
DCB
2
DCC2
4
Defect Detection Circuit
5
DCC1
Built-in Post Filter Amp ( L&R )
40
FOK
16
GC1I
13
CH1O
14
CH1I
19
MUTEI
17
RRC
12
CH2O
11
CH2I
9
GC2I
10
GC2O
Figure 1. Block diagram
M/M-97-P006 1997. 10. 17
2
PRELIMINARY
KB9223 / KB9223-L
RF AMP & SERVO SIGNAL PROCESSOR
PIN CONFIGURATION
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 LPFT TDFCT ATSC SPDLO TEFESPDLTEO FEO SLDVEE FEBIAS SLO SSTOP FOK 40 MIRROR 39 RESET 38 MLT 37 MDATA 36 MCK 35 VSSA 34 EFM 33 ASY 32 ISTAT 31 TRCNT 30 LOCK 29 FGD 28 FS3 27 FLB 26 SMEF 25 MUTEI WDCK GC2O CH2I SMON SMDP GC1O VREG CH2O CH1O VDDA VCCP DCC2 DCC1 FRSH VSSP FSET GC2I GC1I CH1I ISET MCP RRC DCB TG2 FE1 FE2 TE1 TGU DVDD TE2 TZC FDFCT SL+
65 PD1 66 PD2 67 F 68 E 69 PD 70 LD 71 VR 72 VCC 73 RF74 RFO 75 IRF 76 EQO 77 RFI 78 EQC 79 EI 80 GND
KB9223
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Figure 2. Pin configuration
M/M-97-P006 1997. 10. 17
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PRELIMINARY
KB9223 / KB9223-L
PIN DESCRIPTION Table 1. PIN DESCRIPTION Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Symbol MCP DCB FRSH DCC2 DCC1 FSET VDDA VCCP GC2I GC2O CH2I CH2O CH1O CH1I GC1O GC1I RRC VSSP MUTEI ISET VREG WDCK SMDP SMON SMEF FLB
RF AMP & SERVO SIGNAL PROCESSOR
Description Capacitor connection pin for mirror hold Capacitor connection pin for defect Bottom hold Capacitor connection pin for time constant to generate focus search waveform The input pin through capacitor of defect bottom hold output The output pin of defect bottom hold The peak frequency setting pin for focus,tracking servo and cut off frequency of CLV LPF Analog VCC for servo part VCC for post filter Amplifier negative input pin for gain and low pass filtering of DAC output CH2 Amplifier output pin for gain and low pass filtering of DAC output CH2 The input pin for post filter channel2 The output pin for post filter channel2 The output pin for post filter channel1 The input pin for post filter channel1 Amplifier output pin for gain and low pass filtering of DAC output CH1 Amplifier negative input pin for gain and low pass filtering of DAC output CH1 The pin for noise reduction of post filter bias VSS for post filter The input pin for post filter muting control The input pin for current setting of focus search,track jump and sled kick voltage The output pin of regulator The clock input pin for auto sequence The input pin of CLV control output pin SMDP of DSP The input pin for spindle servo ON through SMON of DSP The input pin of provide for an external LPF time constant Capacitor connection pin to perform rising low bandwidth of focus loop
M/M-97-P006 1997. 10. 17
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PRELIMINARY
KB9223 / KB9223-L
Table 1. PIN DESCRIPTION (Continued) Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Symbol FS3 FGD LOCK TRCNT ISTAT ASY EFM VSSA MCK MDATA MLT RESET MIRROR FOK TGU TG2 FEBIAS DVEE PD1 PD2 F E PD LD VR VCC RFRFO
RF AMP & SERVO SIGNAL PROCESSOR
Description The pin for high frequency gain change of focus loop with internal FS3 switch Reducing high frequency gain with capacitor between FS3 pin Sled runaway prevention pin Track count output pin Internal status output pin The input pin for asymmetry control EFM comparator output pin Analog VSS for servo part Micom clock input pin Micom data input pin Micom data latch input pin Reset input pin The mirror output for test The output pin of focus OK comparator The capacitor connection pin for high frequency tracking gain switch The pin for high frequency gain change of tracking servo loop with internal TG2 switch Focus error bias voltage control pin The DVEE pin for logic circuit The negative input pin of RF I/V amplifier1(A+C signal) The negative input pin of RF I/V amplifier2(B+D signal) The negative input pin of F I/V amplifier (F signal) The negative input pin of E I/V amplifier(E signal) The input pin for APC The output pin for APC The output pin of (AVEE+AVCC)/2 voltage VCC for RF part RF summing amplifier inverting input pin RF summing amplifier output pin
M/M-97-P006 1997. 10. 17
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PRELIMINARY
KB9223 / KB9223-L
Table 1. PIN DESCRIPTION (Continued) Pin No. 75 76 77 78 79 80 Symbol IRF EQO RFI EQC EI GND The input pin for AGC The output pin for AGC
RF AMP & SERVO SIGNAL PROCESSOR
Description
Tne input pin for EFM comparision The capacitor connection pin for AGC Feedback input pin of E I/V amplifier for EF Balance control GND for RF part
M/M-97-P006 1997. 10. 17
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PRELIMINARY
KB9223 / KB9223-L
ABSOLUTE MAXIMUM RATINGS Table 2. Absolute Maximum Ratings Characteristic Supply Voltage Power Dissipation Operating Temperature Storage temperature ELECTRICAL CHARACTERISTICS Symbol Vmax PD TOPR TSTG
RF AMP & SERVO SIGNAL PROCESSOR
Value 6 200 -20 ~ +70 -55 ~ +150
Unit V mW
o o
C C
Table 3. Electrical Characteristics (Ta=25C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V )
Characteristic Supply Current High Supply Current Typ Supply Current Low RF Amp Offset Voltage RF Amp Voltage Gain RF THD RF Amp Max. Output Voltage RF Amp Min. Output Voltage Focus Error Amp Offset Voltage Focus Error Amp Auto Offset Voltage Focus Error Amp PD1 Voltage Gain Focus Error Amp PD2 Voltage Gain Focus Error Amp Voltage Difference Focus Error Amp Max. Output Voltage Focus Error Amp Min. Output Voltage AGC Max Gain AGC EQ Gain AGC Gain2 AGC Cpmpress Ratio AGC Frequency Symbol ICCHI ICCTY ICCLO Vrfo Grf Grfmd Vrfpp1 Vrfpp2 Vfeo1 Vfeo2 Gfe1 Gfe2 Gfe Gfepp1 Gfepp2 Gagc Geq Gagc2 Cagc Fagc Test Conditions VCC=6V,No load VCC=5V,No Load VCC=3.4V,No Load input open SG3 f=10KHz,40mVp-p,sine SG3 f=1KHz,40mVp-p,sine SG3 DC 2.7V SG3 DC 2.3V input open WDCH=88.2KHz Pulse ,$841 SG3 f=10KHz,32mVp-p,sine SG3 f=10KHz,32mVp-p,sine Gfe1-Gfe1 SG3 DC 2.7V SG3 DC2.3V SG4 f=500KHz,20mVp-p,sine Gain Difference of Gagc at f=1.5MHz SG4 f=500KHz,0.5Vp-p,sine Gain Difference of Gagc2 at 0.1Vp-p Gain Difference SG4 f=1.5MHz,0.1Vp-p,sine and f=500KHz,0.1Vp-p,sine Output pin 74 pin 74 pin 74 pin 74 pin 74 pin 59 pin 59 pin 59 pin 59 pin 59 pin 59 pin 59 pin 76 pin 76 pin 76 pin 76 pin 76 Min 20 12 10 -80 25.1 3.8 -450 -35 27 27 -3 4.4 16 0 3.5 0 -1.5 Typ 40 30 25 0 28.1 -250 0 30 30 0 19 1 6 2.5 0 Max 60 48 40 +80 31.1 5 1.2 -50 35 33 33 +3 0.6 22 2 9 5 2.5 Unit mA mA mA mV dB % V V mV mV dB dB dB V V dB dB dB dB dB
M/M-97-P006 1997. 10. 17
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PRELIMINARY
KB9223 / KB9223-L
RF AMP & SERVO SIGNAL PROCESSOR
Table 3. Electrical Characteristics (Continued) (Ta=25C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V )
Characteristic Tracking Error Offset Voltage Tracking Error Amp Voltage Gain F Tracking Error AmpVoltage Gain E Tracking Error Amp Voltage Gain Difference Tracking Error Amp Maximum Output Voltage H Tracking Error Amp Minimum Output Voltage L Tracking Error Amp Gain up F Tracking Error Amp Gain up E Tracking Gain Normal Tracking F Gain 1 Tracking F Gain 2 Tracking F Gain 3 Tracking F Gain 4 Tracking E Balance Normal Tracking E Balance 1 Tracking E Balance 2 Tracking E Balance 3 Tracking E Balance 4 Tracking E Balance 5 FGFN-FGF1 FGFN-FGF2 FGFN-FGF3 FGFN-FGF4 TBE5 - TBE4 TBE4 - TBE3 TBE3 - TBE2 TBE2 - TBE1 APC PSUB Voltage 1 APC PSUB Voltage 2 Symbol Vteo Gtef Gtee Gte Vtepp1 Vtepp2 Tguf Tgue Fgfn Fgf1 Fgf2 Fgf3 Fgf4 Tben Tbe1 Tbe2 Tbe3 Tbe4 Tbe5 FG1 FG2 FG3 FG4 TB1 TB2 TB3 TB4 Vapc1 Vapc2 Test Conditions $800,$820,input open $800,$820 SG3 0.3Vp-p,10KHz,sine SG3 0.3Vp-p,40KHz,sine Gtef-Gtee DG3 DC 4.5V SG3 DC 0.5V $830 SG3 0.3Vp-p,10KHz,sine $830 SG3 0.3Vp-p,10KHz,sine SG3 0.3Vp-p,10KHz,sine,$820 SG3 0.3Vp-p,10KHz,sine,$821 SG3 0.3Vp-p,10KHz,sine,$822 SG3 0.3Vp-p,10KHz,sine,$824 SG3 0.3Vp-p,10KHz,sine,$824 SG3 0.3Vp-p,10KHz,sine,$800 SG3 0.3Vp-p,10KHz,sine,$801 SG3 0.3Vp-p,10KHz,sine,$802 SG3 0.3Vp-p,10KHz,sine,$804 SG3 0.3Vp-p,10KHz,sine,$808 SG3 0.3Vp-p,10KHz,sine,$810 LDON,$853,PN=open, SG4 GND+85mV LDON,$853,PN=open, SG4 GND+185mV Output pin 54 pin 54 pin 54 pin 54 pin 54 pin 54 pin 54 pin 54 pin 54 pin 54 pin 54 pin 54 pin 54 pin 54 pin 54 pin 54 pin 54 pin 54 pin 54 pin 70 pin 70 Min -50 2.1 -0.75 -0.25 3.5 8.0 5.3 2.1 0.1 -1.7 -5.0 -9.2 -0.27 -0.51 -0.74 0.17 1.03 2.63 0 0.5 2.0 3.0 0.6 -0.14 -0.57 -0.77 3.8 Typ 0 5.1 2.25 2.75 11.0 8.3 5.1 3.1 1.3 -2.0 -6.2 2.27 2.51 2.74 3.17 4.03 5.63 1.5 2.0 3.25 4.25 1.6 0.86 0.43 0.23 Max +50 8.1 5.25 5.75 1.5 14.0 11.3 8.1 6.1 4.3 1.0 -3.2 5.27 5.51 5.74 6.17 7.03 8.63 3 3.5 4.5 5.5 2.6 1.86 1.43 1.23 1.2 Unit mV dB dB dB V V dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB V V
M/M-97-P006 1997. 10. 17
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PRELIMINARY
RF AMP & SERVO SIGNAL PROCESSOR
Table 3. Electrical Characteristics (Continued) (Ta=25C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V )
Characteristic APC NSUB Voltage 1 APC NSUB Voltage 2 APC LD Off Voltage 1 APC LD Off Voltage 2 APC Maximum Output Current H APC Minimum Output Current L Mirror Maximum Output Voltage H Mirror Minimum Output Voltage L Mirror Minimum Operating Frequency Mirror Maximum Operating Frequency Mirror AM Frequency Characteristic Symbol Vapc3 Vapc4 Vapc5 Vapc6 Vapc7 Vapc8 Vmirh Vmirl Fmirh Fmirb Fmir Test Conditions LDON,$857,PN=2.5V, SG4 GND+95mV LDON,$857,PN=2.5V, SG4 GND+165mV LDOFF,$85C,PN=open,SG4 2.5V LDOFF,$858,PN=2.5V.SG4 2.5V LDON,$854,PN=open, SG4 GND + 185mV LDON,$854,SG4 GND + 85mV SG4 2.1V+0.8Vp-p,1KHz,sine SG4 2.1V+0.8Vp-p,1KHz,sine SG4 2.1V+0.8Vp-p,900Hz,sine SG4 2.1V+0.8Vp-p,30KHz,sine SG4 2.1V+0.8Vp-p 600Hz,fc=500KHz 55% modulation SG4 2.1V+0.2Vp-p,10KHz,sine SG4 2.1V+1.8Vp-p,10KHz,sine SG4 2.25V~2.0V,DCsweep, 10mV step SG4 DC 1.5V SG4 DC 2.5V $863,SG3 2.520V+0.04Vp-p, f=1Khz,sine $863,SG3 2.520V+0.04Vp-p, f=1Khz,sine SG2 2.5V+0.1Vp-p,1KHz,sine SG2 2.5V+0.1Vp-p,1KHz,sine SG2 2.5V+0.1Vp-p,1KHz,sine SG3 2.520 V+0.04Vp-p, 1KHz,sine SG3 2.520V+0.04Vp-p, 2KHz,sine SG 3 2.510V+0.020Vp-p, 1KHz,sine Output pin 70 pin 70 pin 70 pin 70 pin 70 pin 70 pin 39 pin 39 pin 39 pin 39 pin 39 Min 3.8 4.0 2.5 4.3 30 -
KB9223 / KB9223-L
Typ 550 75 400
Max 1.2 1.0 2.5 0.7 900 600
Unit V V V V V V V V Hz KHz Hz
Mirror Minimum Input Voltage Mirror Maximum Input Voltage FOK Threshold Voltage FOK Output Voltage H FOK Output Voltage L Defect Output Voltage H Output Voltage L Focus Loop Mute Tracking Loop Mute Interruption Defect Bottom Voltage Defect Max Freq. Voltage Defect Minimum Input Voltage
Vmir Vmih Vfokt Vfokh Vfokl Vdfcth Vdfcth Fmute Tmute Imute Fdfct1 Fdfct2 Vdfct1
pin 39 pin 39 pin 40 pin 40 pin 40 pin 41 pin 41 pin 48 pin 50 pin 50 pin 41 pin 41 pin 41
1.8 -420 4.3 4.3 -100 -100 -100 2.0 -
0.1 -360 0 0 0 670 4.7 0.3
0.2 -300 0.7 0.7 100 120 120 1000 0.5
V V mV V V V V mV mV mV Hz KHz V
M/M-97-P006
ELECTRONICS
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1997. 10 .17
PRELIMINARY
KB9223 / KB9223-L
RF AMP & SERVO SIGNAL PROCESSOR
Table 3. Electrical Characteristics (Continued) (Ta=25C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V )
Characteristic Defect Maximum Input Voltage EFM Duty Voltage 1 EFM Duty Voltage 2 EFM Minimum input Voltage EFM Maximum input Voltage EFM Maximum Operating Frequency FZC Threshold Voltage ATSC Threshold Voltage 1 ATSC Threshold Voltage 2 TZC Threshold Voltage SSTOP Threshold Voltage Tracking gain window voltage Tracking gain window range Tracking balance window voltage Tracking balance window range Vreg Threshold Voltage Center Voltage VREF Current Drive Voltage 1 VREF Current Drive Voltage 2 Post CH1 Freq. Characteristic Post CH2 Freq. Characteristic Post CH1 Mute Post CH2 Mute Focus Loop DC Gain Focus Off Offset Focus On Offset Focus Auto Offset Symbol Vdfct2 Defm1 Defm2 Vefm1 Vefm2 Fefm Vfzc Vatsc1 Vatsc2 Vtzc Vsstop VtGW VTGW2 VTBW VTBW2 Vreg VCVO VCVO1 VCVO2 Fpos1 Fpos2 Mute1 Mute2 Gf Vosf1 Vofs2 Vaof Test Conditions SG32.535V+0.070Vp-p, 1KHz,sine SG4 2.5V+0.75Vp-p, 750KHz,sine SG42.75V+0.75Vp-p, 750KHz,sine SG4 2.5V+0.12Vp-p, 750KHz,sine SG4 2.5V+1.8Vp-p,750KHz,sine SG4 2.5V+0.75Vp-p,4MHz DC 2.5V+38mV,100mV $10,SG2 DC 2.5V-6mV,-45mV SG2 DC 2.5V+6mV,+45mV $20,SG2 DC 2.5V-20mV,+20mV $30,SG2 DC 2.5V-71mV,-30mV $840+$830 SG2 2.5V 2.9V 5mV DC $848+$830 SG2 2.5V 5mV DC sweep $844+$810 SG2 2.555V ~ 2.475V 5mV DC sweep $844+$810 SG2 2.555V ~ 2.470V 5mV DC sweep 2.5V Reference 2.5V Reference 2.5V Reference SG1 2.5V+1Vp-p,40KHz,sine SG1 2.5V+1Vp-p,40KHz,sine Mute=5V SG1 2.5V+1Vp-p,1KHz,sine Mute=5V SG1 2.5V+1Vp-p,1KHz,sine $08,SG2 DC 2.6V,2.4V average $00 $08,DC 2.5V $842,WDCK,after100ms Output pin 41 pin 32 pin 32 pin 33 pin 33 pin 33 pin 31 pin 31 pin 33 pin 31 pin 31 pin 30 pin 30 pin 31 pin 31 pin 21 pin 71 pin 71 pin 71 pin 13 pin 12 pin13 pin 12 pin 48 pin 48 pn 48 pin 48 Min 1.8 -50 0 1.8 4 39 -67 7 -30 -100 200 100 -25 -25 3.2 -100 -100 -100 -4.5 -4.5 19.0 -100 0 -65 Typ 0 50 69 -32 32 0 -50 250 150 15 15 3.4 0 0 0 -3.0 -3.0 21.5 0 250 0 Max 50 100 0.12 100 -7 67 30 -30 300 200 55 55 3.6 100 100 100 -1.5 -1.5 -35 -35 24.0 100 500 65 Unit V mV mV V V MHz mV mV mV mV mV mV mV mV mV V mV mV mV dB dB dB dB dB mV mV mV
M/M-97-P006 1997. 10. 17
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PRELIMINARY
KB9223 / KB9223-L
RF AMP & SERVO SIGNAL PROCESSOR
Table 3. Electrical Characteristics (Continued) (Ta=25C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V )
Characteristic Focus Output Voltage H Focus Output Voltage L Focus Output Drive Voltage H Focus Output Drive Voltage L Focus Oscillation Voltage Focus Feed Through Focus AC Gain 1 Focus AC Phase 1 Focus AC Gain 2 Focus AC Phase 2 Focus Search Voltage1 Focus Search Voltage2 Focus Loop Total Gain Tracking DC Gain Tracking Off Offset Tracking On Offset Tracking Oscillation Voltage Tracking gain boost for ATSC Tracking gain boost on LOCK (L) Tracking Output Voltage H Tracking Output Voltage L Tracking Output Drive Voltage H Tracking Output Drive Voltage L Tracking Jump Voltage 1 Tracking Jump Voltage 2 Tracking Feed Through Tracking AC Gain 1 Symbol Vfoh1 Vfol1 Vfoh2 Vfol2 Vosc Gff Gfa1 Pfa1 Gfa2 Pfa2 Vfs1 Vfs2 Gftg Gto Vost1 Vost2 Vosa1 Gatsc Glock Vth1 Vtl1 Vth2 Vtl2 Vtj1 Vtj2 Gtf Gta1 Test Conditions $08,DC 3.0V $08,DC 2.0V $08,DC 3.0V $08,DC 2.0V $08,DC2.5V Gain Difference at Servo on and off $08, SG2 2.5V+0.1Vp-p,1.2KHz,sine $08, SG2 2.5V+0.1Vp-p,1.2KHz,sine $08, SG2 2.5V+0.1Vp-p,2.7KHz,sine $08, SG2 2.5V+0.1Vp-p,2.7KHz,sine $30+$02 $30+$03 Focus PD gain + Focus loop DC gain $25 SG2 DC 2.3V,2.7V average gain $20 SG2 DC 2.5V,$25 $25,SG2 DC2.5V 2.5V+0.1Vp-p,1KHz,sine 2.5V+0.1Vp-p,1KHz,sine $25,SG2 DC 1.0V $25SG2 ,DC 4.0V $25,SG2 DC2.0V $25, SG2 DC3.0V $2C $28 Gain Difference at Tracking servo on and off $10,$25,SG2 2.5V+0.1Vp-p, 1.2KHz,sine Output pin 48 pin 48 pin 48 pin 48 pin 48 pin 48 pin 48 pin 48 pin 48 pin 48 pin 48 pin 48 pin 48 pin 50 pin 50 pin 50 pin 50 pin 50 pin 50 pin 50 pin 50 pin 50 pin 50 pin 50 pin 50 pin 50 pin 50 Min 4.40 3.68 0 19.0 40 14.0 40 -0.64 0.36 49.5 13.5 -100 -100 0 17.5 17.5 4.48 3.68 -0.64 0.36 9.0 Typ 100 23.0 65 18.5 65 -0.50 0.50 51.5 15.5 0 0 100 20.5 20.5 -0.5 0.5 12.5 Max 0.60 1.32 200 -35 27.0 90 23.0 90 -0.36 0.64 53.5 17.5 100 120 200 23.5 23.5 0.52 1.32 -0.36 0.64 -39 16.0 Unit V V V V mV dB dB deg dB deg V V dB dB mV mV mV dB dB V V V V V V dB dB
M/M-97-P006 1997. 10. 17
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PRELIMINARY
KB9223 / KB9223-L
RF AMP & SERVO SIGNAL PROCESSOR
Table 3. Electrical Characteristics (Continued) (Ta=25C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V )
Characteristic Tracking AC Phase 1 Tracking AC Gain 2 Tracking AC Phase 2 Tracking Loop Gain Sled DC Gain Sled Feed Through Symbol Pta1 Gta2 Pta2 Gtrt Gsl Gslf Test Conditions $10,$25,SG2 2.5V+0.1Vp-p, 1.2KHz,sine $10,$25,SG2 2.5V+0.1Vp-p, 2.7KHz,sine $10,$25,SG2 2.5V+0.1Vp-p, 2.7KHz,sine tracking Amp F gain+ servo DC gain SG2 DC 2.6V,2.4V Gain Difference at sled servo on and off SG2 2.5V+0.1Vp-p,1.2KHz,sine $25,SG2 DC 2.9V $25,SG2 DC 2.1V $25,SG2 DC 2.9V $25,SG2 DC 2.1V $22 $23 $F0 SG1 DC 2.6V,2.4V, average gain $F3 SG1 DC 2.6V,2.4V, average gain $F0, SG1 DC 3.5V $F0, SG1 DC 1.5V $F0,SG1 DC 3.5V $F0,SG1 DC 1.5V $F0,SG1 2.5V+0.2Vp-p, 2KHz,sine $F0,SG1 2.5V+0.2Vp-p, 2KHz,sine Output pin 50 pin 50 pin 50 pin 43 pin 43 Min -140 17.5 -195 18.5 20.5 Typ -115 21.5 -150 20.5 22.5 Max -90 25.5 -100 22.5 24.5 -34 Unit deg dB deg dB dB dB
Sled Output Voltage H Sled Output Voltage L Sled Output Drive Voltage H Sled Output Drive Voltage L Sled Forward Kick Voltage Sled Reverse Kick Voltage Spindle Normal Speed Gain Spindle Double Speed Gain Spindle Output Voltage H Spindle Output Voltage L Spindle Output Drive Voltage H Spindle Output Drive Voltage L Spindle AC Gain Spindle AC Phase
Vslh1 Vsll1 Vslh2 Vsll2 Vsk1 Vsk2 Gsp Gsp2 Gsph1 Gspl1 Gsph2 Gspl2 Gspa Pspa
pin 43 pin 43 pin 43 pin 43 pin 43 pin 43 pin 46 pin 46 pin 46 pin 46 pin 46 pin 46 pin 46 pin 46
4.48 3.68 0.38 -0.75 14.0 19.0 4.48 3.68 -7.0 -120
0.60 -0.6 16.5 23.0 -3.5 -90
0.52 1.32 0.75 -0.38 19.0 27.0 0.52 1.32 0 -60
V V V V V V dB dB V V V V dB deg
M/M-97-P006 1997. 10. 17
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PRELIMINARY
RF AMP & SERVO SIGNAL PROCESSOR
Table 3. Electrical Characteristics (Continued) (Ta=25C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V )
Characteristic FOCUS output voltage H FOCUS output voltage L FOCUS SEARCH voltage 1 FOCUS SEARCH voltage 2 TRACKING on OFFSET TRACKING output voltage H TRACKING output voltage L TRACKING jump voltage 1 TRACKING jump voltage 2 SLED output voltage H SLED output voltage L SLED forward kick voltage SLED reverse kick voltage SPINDLE output voltage H SPINDLE output voltage L RF amp OFFSET voltage Tracking error offset RF amp output voltage H RF amp output voltage L FOCUS error output voltage H FOCUS error output voltage L Tracking error output voltage Tracking error output voltage APC output voltage 1L APC output voltage 2L APC output voltage 3L APC output voltage 4L APC output voltage 5L APC output voltage 6L FOK threshold voltage Post Filter Output Voltage max. 1 Symbol Vfh1l Vfl1l Vfs1l Vfs2l Vost21 Vth1l Vtl1l Vtj1l Vtj2l Vslh1l Vsll1l Vsk1l Vsk2l Vsph1l Vspl1l Vrfol Vteol Vrfpp1l Vrfpp2l Vfepp1l Vfepp2l Vtepp1l Vtepp2l Vapc1l Vapc2l Vapc3l Vapc4l Vapc5l Vapc6l Vfoktl Vpom1 SG1 2.5V+3.2Vp-p,1KHz, within THD 1% VDD, DVDD, VCC = +3.4V Low Voltage Test for Servo Part & RF part : the test method is the same as 5V test Test Conditions Output pin 48 pin 48 pin 48 pin 48 pin 50 pin 50 pin 50 pin 50 pin 50 pin 43 pin 43 pin 43 pin 43 pin 46 pin 46 pin 74 pin 54 pin 74 pin 74 pin 59 pin 59 pin 54 pin 54 pin 70 pin 70 pin 70 pin 70 pin 70 pin 70 pin 40 pin 13 Min 2.88 -
KB9223 / KB9223-L
Typ -0.50 0.50 0 -0.50 0.50 0.60 -0.60 0 0 -360 1.3
Max 0.68 -0.36 0.64 +120 0.68 -0.36 0.64 0.68 0.75 -0.38 0.68 +80 +50 0.6 0.6 1.2 1.2 1.2 1.1 -300 -
Unit V V V V mV V V V V V V V V V V mV mV V V V V V V V V V V V V V Vrms
-0.64 0.36 -100 2.88 -0.64 0.36 2.88 0.38 -0.75 2.88 -80 -50 2.8 2.8 2.2 2.5 2.5 2.7 -420 1.1
M/M-97-P006
ELECTRONICS
14
1997. 10 .17
PRELIMINARY
KB9223 / KB9223-L
RF AMP & SERVO SIGNAL PROCESSOR
Table 3. Electrical Characteristics (Continued) (Ta=25C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V )
Characteristic Post Filter Output Voltage max. 2 Total Harmonic Distoration 1 Total Harmonic Distoration 1 Total Harmonic Distoration 1 Total Harmonic Distoration 1 Total Harmonic Distoration 1 Total Harmonic Distoration 2 Total Harmonic Distoration 2 Total Harmonic Distoration 2 Total Harmonic Distoration 2 Total Harmonic Distoration 2 Frequency Characteristics 1 Frequency Characteristics 1 Frequency Characteristics 1 Frequency Characteristics 1 Frequency Characteristics 1 Frequency Characteristics 2 Frequency Characteristics 2 Frequency Characteristics 2 Frequency Characteristics 2 Frequency Characteristics 2 Crosstalk 1 Crosstalk 1 Crosstalk 1 Crosstalk 2 Crosstalk 2 Crosstalk 2 Characteristic Signal to Noise Ratio 1 Signal to Noise Ratio 2 Channel Balance Symbol Vpom2 THD11 THD12 THD13 THD14 THD15 THD21 THD22 THD23 THD24 THD25 fv11 fv12 fv13 fv14 fv15 fv21 fv22 fv23 fv24 fv25 CT11 CT12 CT13 CT21 CT22 CT23 Symbol S/N 1 S/N 2 CB Test Conditions SG1 2.5V+3.2Vp-p,1KHz, within THD 1% SG1 f=100Hz,0dBm SG1 f=1KHz,0dBm SG1 f=10KHz,0dBm SG1 f=16KHz,0dBm SG1 f=20KHz,0dBm SG1 f=100Hz,0dBm SG1 f=1KHz,0dBm SG1 f=10KHz,0dBm SG1 f=16KHz,0dBm SG1 f=20KHz,0dBm SG1 f=100Hz,0dBm SG1 f=1KHz,0dBm SG1 f=10KHz,0dBm SG1 f=16KHz,0dBm SG1 f=20KHz,0dBm SG1 f=100Hz,0dBm SG1 f=1KHz,0dBm SG1 f=10KHz,0dBm SG1 f=16KHz,0dBm SG1 f=20KHz,0dBm SG1 100Hz,0dBm,ratio on Ch2 SG1 1KHz,0dBm,ratio on Ch2 SG1 10KHz,0dBm,ratio on Ch2 SG1 100Hz,0dBm,ratio on Ch1 SG1 1KHz,0dBm,ratio on Ch1 SG1 10KHz,0dBm,ratio on Ch1 Test Conditions DC 2.5V 0dbm,ratio on Noise DC 2.5V 0dbm,ratio on Noise Gain Difference Ch1 and Ch2 Output pin 12 pin 13 pin 13 pin 13 pin 13 pin 13 Pin 12 Pin 12 Pin 12 Pin 12 Pin 12 pin 13 pin 13 pin 13 pin 13 pin 13 Pin 12 Pin 12 Pin 12 Pin 12 Pin 12 pin 13 pin 13 pin 13 pin 12 pin 12 pin 12 Output pin 13 pin 12 Min 1.1 -0.1 -0.25 -0.5 -1.0 -1.5 -0.1 -0.25 -0.5 -1.0 -1.5 70 65 60 70 65 60 Min 73 73 -0.1 Typ 1.3 0.01 0.01 0.05 0.1 0.1 0.01 0.01 0.05 0.1 0.1 0 0 0 0 0 0 0 0 0 0 80 75 65 80 75 65 Typ 80 80 0 Max 0.05 0.05 0.1 0.2 0.2 0.05 0.05 0.1 0.2 0.2 0.1 +0.25 0.5 1.0 1.5 0.1 +0.25 0.5 1.0 1.5 Max +0.1 Unit Vrms % % % % % % % % % % dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB Unit dB dB dB
M/M-97-P006 1997. 10. 17
14
PRELIMINARY
KB9223 / KB9223-L
RF AMP & SERVO SIGNAL PROCESSOR
Table 3. Electrical Characteristics (Continued) (Ta=25C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V )
Characteristic Post filter output voltage mix.1L Post filter output voltage mix. 2L Total harmonic distortion 1L Total harmonic distortion 1L Total harmonic distortion 1L Total harmonic distortion 1L Total harmonic distortion 1L Total harmonic distortion 2L Total harmonic distortion 2L Total harmonic distortion 2L Total harmonic distortion 2L Total harmonic distortion 2L Frequency Characteristics 1L Frequency Characteristics 1L Frequency Characteristics 1L Frequency Characteristics 1L Frequency Characteristics 1L Frequency Characteristics 2L Frequency Characteristics 2L Frequency Characteristics 2L Frequency Characteristics 2L Frequency Characteristics 2L Cross talk 1L Cross talk 1L Cross talk 1L Cross talk 2L Cross talk 2L Cross talk 2L Signal to noise ratio 1L Signal to noise ratio 2L Channel balance L Symbol Vpom1L Vpom2L THD11L THD12L THD13L THD14L THD15L THD21L THD22L THD23L THD24L THD25L fv11L fv12L fv13L fv14L fv15L fv21L fv22L fv23L fv24L fv25L CT11L CT12L CT13L CT21L CT22L CT23L S/N1L S/N2L CBL VDD, DVDD, VCC VCCP= +3.4V Low voltage test for post filter. The test method is the same as 5V test except for input signal : SG1 1.7V + 1.55Vp-p Test Conditions Output pin 13 pin 12 pin 13 pin 13 pin 13 pin 13 pin 13 pin 12 pin 12 pin 12 pin 12 pin 12 pin 13 pin 13 pin 13 pin 13 pin 13 pin 12 pin 12 pin 12 pin 12 pin 12 pin 13 pin 13 pin 13 pin 12 pin 12 pin 12 pin 13 pin 12 Min 0.5 0.5 -0.1 -0.25 -0.5 -1.0 -1.5 -0.1 -0.25 -0.5 -1.0 -1.5 67 62 57 67 62 57 67 67 -0.1 Typ 0.55 0.55 0.01 0.01 0.05 0.1 0.1 0.01 0.01 0.05 0.1 0.1 0 0 0 0 0 0 0 0 0 0 80 75 65 80 75 65 80 80 0 Max 0.05 0.05 0.1 0.2 0.2 0.05 0.05 0.1 0.2 0.2 0.1 +0.25 0.5 1.0 1.5 0.1 +0.25 0.5 1.0 1.5 +0.1 Unit Vrms Vrms % % % % % % % % % % dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
Note1) The notation $ means hexa decimal of micom command Note2) Low voltage test items only refer to KB9223-L M/M-97-P006 1997. 10. 17
15
RF AMP & SERVO SIGNAL PROCESSOR
PRELIMINARY
VC(2.5V)
VCC(5V)
GND(0V)
SG2 DC AC
SW22 VERTOR_TEST_IN SG-_D10 SW23 VERTOR_TEST_IN SG-_D11
0.01UF
96K
SW19 12 0.25K 0.25K 0.25K 13K 13K 13K 12 1 2 13K
SW17
SW16 1
SW15
VECTOR_TEST_IN
VERTOR_TEST_IN
0.01UF
+
+
2 0.25K
SW29
SW27
SW26
SW25
SW24
100K
SW28
100K
200K
100K
200K
SPDLO
TDFCT
FEBIAS
10K SW30 10K SW31 DC 390K SW32 SG3 390K SW33 AC
SSTOP
FDFCT
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 ATSC SPDLDVDD DVEE LPFT TGU TEO FEO SLO TG2 TZC FE1 FE2 TE1 TE2 SL+ TEFESL-
5K
SW14
SW21
SW20
SW18
SW13
60K
SG_D12
65 PD1 66 PD2 67 F 68 E 69 PD 70 LD 71 VR 72 VCC
FOK 40 MIRROR 39 RESET 38 MLT 37 MDATA 36 MCK 35 VSSA 34 EFM 33
VECTOR_TEST_IN VECTOR_TEST_IN VECTOR_TEST_IN VECTOR_TEST_IN VECTOR_TEST_IN VECTOR_TEST_IN
SG-D8
SG-D7
SG-D6
SW34 3K SW35 3K SW36 0.5K SW37
+ 33UF
SG-D4
M/M-97-P006
SG-D3
Figure 3. Test Circuit
SG-D5
16
0.5K SW38
SW-VC
2PF 22K
73 RF74 RFO 75 IRF 76 EQO 77 RFI 78 EQC 79 EI MUTEI WDCK GC2I GC2O FSET GC1I CH1I CH2I ISET MCP RRC DCB 80 GND SMDP GC1O VREG VDDA VCCP CH2O CH1O DCC2 DCC1 FRSH VSSP
ISTAT 31 VECTOR_TEST_OUT
VECTOR_TEST_OUT TRCNT 30
DC SW40 SG4 SW41 + 1uF SW42
AC
0.01UF SW39
LOCK 29 FGD 28 FS3 27 FLB 26 SMON SMEF 25
SW10
+
KB9223
SW11
ASY 32
11K 0.01UF
VECTOR_TEST_IN
SG-D2 SW9 SW8
1000PF
KB9223 / KB9223-L
1
2
1000PF
3
SW44.7UF + 3300PF
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
27K 5.6K 10PF 3300PF 4.7UF 27K 0.01PF 5.6K 10PF 4.7UF 27K 240K
330PF 330PF
27K 4.7UF
+
VECTOR_TEST_IN
SW3
SW6
3.3UF
0.1UF
0.001UF
3.3UF
5.6K 5.6K 510K
+ + +
+
+
TEST CIRCUIT
SW1
10K
SWP1
DC SG1
SWP2
SG-D1
AC
SW2
10K
SW5
5.6K 5.6K
SW7
1997. 10. 17
PRELIMINARY
KB9223 / KB9223-L
FUNCTION DESCRIPTION 1.RF Amp Block 1.1 RF Amplifier
RF AMP & SERVO SIGNAL PROCESSOR
The optical currents inputted through pins PD1(A+C) and PD2(B+D) are converted into voltages through I-V amp, and they are added to RF summing amp. The voltage, converted from the photo diode (A+B+C+D) signal, is outputted through RFO(pin74) and the eye pattern can be checked at this pin.
58K PD1 65
+ VC
VA I-V amp(1)
10K
74 + VC RF summing amp
RFO
58K PD2 66
+ VC
VB I-V amp(2)
10K 73
RF-
Figure 4. RF amp circuit 1.2 Focus Error Amp The output of the focus error amp is the difference between I-V amp(1) output VA and RF I-V amp(2) output VB. The focus error bias voltage applied to the (+) of focus error amp can be changed by output voltage of D/A converter as shown in diagram, so that the offset of focus error amp can be adjusted automatically by controlling 5 bits counter switches. Focus error bias can be adjusted from the range of +100mV ~ -100mV by connecting the resistor on pin 63 (FEBIAS).
164K VB > VA > sev-stopb FEBIAS 63 sev-stop <5 Bit Counter> 3K
X1 X2 X4 X8 X16
32K 32K
59 + 160K
FE1
SW1
4K
+ FEBIAS vc
fcmpo
+
fe-stopb
Figure 5. Focus error amp circuit note1> VA and VB refer to output signal of PD1 and PD2 I/V amp. note2> sev-stopb,sev-stop,fe-stopb and fcmpo are internal signals
M/M-97-P006 1997. 10. 17
17
PRELIMINARY
KB9223 / KB9223-L
1.3 Tracking Error Amp
RF AMP & SERVO SIGNAL PROCESSOR
The optical currents detected from the side photo diode (E and F) pf pick-up are inputted to the E and F pin and converted into voltage signals by E I-V and F I-V amp. The output of tracking error amp generates the difference between E I-V AMP and F I-V AMP voltage output. The E-F balance can be adjusted by modifying the gain of E I-V AMP, and the tracking gain can be adjusted automatically by controlling the peak voltage at pin TE2 by micom program.
TE1
TE2
54
53
55
LPFT
F
67 68
I-V AMP I-V AMP
-
+
Balance Window Comp
To ISTAT
E
13K
16K
7.5K
1.5K
79
220K 110K 56K 27K 75K 13K
3.3K
EI
Gain Window Comp
To ISTAT To TRCNT
BAL < 4 : 0 >
GAIN_UP/DOWN GAIN < 3 : 0 >
Figure 6. Tracking error amp circuit
1.4 Focus OK Circuit The FOK is the output. The focus OK circuit generates a timing window to enable focus servo operation from focus search status. When the difference of the RFO (pin74)signal and DC coupled signal IRF(pin75) are above the predefined voltage the Focus OK circuit output (pin40) becomes active(High output). The predefined voltage is -0.39V
40K 40K RFO IRF 74 75 40K
+
57K
40 90K +
FOK
VC+0.625V
Figure 7. Focus OK circuit
M/M-97-P006 1997. 10. 17
18
PRELIMINARY
KB9223 / KB9223-L
1.5 Mirror Circuit
RF AMP & SERVO SIGNAL PROCESSOR
IRF signal is amplified by the mirror amp, and the peak and bottom component of amplified signal are detected by peak and bottom hold circuit. The peak hold circuit covers traverse signal of up to 100KHz component and bottom hold circuit capable of covering the envelope frequency of disc rotation. The time constant for the mirror hold must be sufficiently larger than that of the traverse signal.
38K IRF 75 17K 2.5K Peak and Bottom Hold + 17K
1.5K 1 MCP
+
+ 96K
19K
+ 39 MIRROR
-
Figure 8. Mirror Circuit
1.6 EFM Comparator The EFM comparator converts a RF signal into a binary signal. Beacuse the asymmetry generated due to variations in disc manufacturing can not be eliminated by the AC coupling alone, this circuit uses to control reference voltage of EFM comparator for eliminating asymmetry.
40K RFI 77 + 1 EFM
100K + 19K + 20K 39 ASY
100K
85K
Figure 9. EFM Comparator & asymmetry circuit
M/M-97-P006 1997. 10. 17
19
PRELIMINARY
KB9223 / KB9223-L
1.7 Defect Circuit
RF AMP & SERVO SIGNAL PROCESSOR
The RFO signal bottom, after being inverted, is held with two time constants of long and short. The short time-constant bottom hold is done for a disc mirror defect more than 0.1msec, the long timeconstant bottom hold is done with the mirror level prior to the defect. By differentiating this with a capacitor coupling and shifting the level, both signals are compared to generate the mirror defect detection signal.
DCC1 5 4
DCC2
75K
RFO
75
37.5K 28K
+
BOTTOM HOLD
75K BOTTOM VC+0.6254V HOLD 43K +
-
DFCT 41
SSTOP/DFCT
2 DCB
Figure 10. Defect Circuit
1.8 APC (Auto Power Control) Circuit The laser diode has large negative temperature characteristic in its optical output when driven with a constant current on laser diode. Therefore, the output on processing monitor photo diode, must be a controlled current for getting regular output power, thus the APC (Auto Power Control) circuit is composed.
PN (From micom command) PD 69 43.5K + 150K +
0.75K 70 LD
150K
150K
300K
1.25V
5.5K
LDON (From micom command)
Figure 11. APC Circuit
M/M-97-P006 1997. 10. 17
20
PRELIMINARY
KB9223 / KB9223-L
1.9 AGC Stability Circuit
RF AMP & SERVO SIGNAL PROCESSOR
The AGC block is the function used to maintain the constant level of RF peak to peak voltage. After the operation of RF envelop detection and comparing with reference voltage, RFO level is kept stable in 1Vpp, and inputted to EFM Slice.
IRF
75
VCA
EQUALIZE
78
EQC
76 EQO
Figure 12. AGC block 1.10 Post Filter The adjustment of audio output gain and the integration of possible de-emphasis output are executed by this circuit. This block has amps of 2 channel for gain and filter setting and mute pin for audio signal muting.
CH2I VCC
+ 12 CH2O
25K
GC2I
+
+ GC1I 25K
10 GC2O
+
15 GC1O
+
CH1I
13 CH1O
-
19 MUTEI
Figure 13. Post Filter circuit
1.11 Center Voltage Generation Circuit The center voltage is generated by voltage divide using resistor . Figure 14. Center Voltage Generation Circuit
VCC
30K
71 VR +
30K
M/M-97-P006 1997. 10. 17
21
PRELIMINARY
KB9223 / KB9223-L
2.Servo Block 2.1 Focus Servo Block
RF AMP & SERVO SIGNAL PROCESSOR
When defect is "H"(the defect signal is detected), the focus servo loop is muting in case of focus phase compensation. At this time, the focus error signal is outputted through the low pass filter formed by connecting a capacitor(0.1uF) and a built-in 470K resistor to the FDFCT pin(pin 60). Accordingly, the focus error output is held at the error value just before defect error during defect occurring. The peak frequency of focus loop phase compensation is at about 1.2KHz when the resistor connected to FSET pin(pin 6) is 510K, and it is inversely proportional to the resistor connected to the FSET pin. While the focus search is operating, the FS4 switch is on and then the focus error signal is isolated, accordingly the focus search signal is outputted by FEO pin(pin 48). When the FS2 switch is on(focus on), the focus servo loop is on and the focus error signal from FE2 pin(pin 58) is outputted through the focus servo loop.
3.6K 60K
VC
+
FSCMPO
+
FZCI
+
48K
48
FEO
FE2
58
470K
20K
Focus Phase Compensation
92K
X4
X3
X2
X1
FDFCT
60
FS4B 130K FS2B
40K
+
FE-
47
DFCTI 470K FGD 40K 10K 50K 3.6K PS 4 FS1 46K 580K FS3 X1 X2 X3 X4 0 0 1 1 3 0 1 0 1
28
FS3
27 +
26
FLB
6
FSET
3
FRCH
Figure 15. Focus servo block
M/M-97-P006 1997. 10. 17
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PRELIMINARY
KB9223 / KB9223-L
2.2 Tracking Servo Block
RF AMP & SERVO SIGNAL PROCESSOR
During detection of defect, the tracking error signal is outputted through the tracking servo loop after passing the low pass filter formed by connecting a capacitor(0.1uF) and a built-in 470K resistor to the TDFCT pin(pin57) in case of tracking phase compensation. The value of tracking gain up/down can be controlled by TGU and TG2 pin. The peak frequency of tracking loop phase compensation, the dynamic range and offset of opamp can be adjusted by changing the value of resistor connected to FSET pin same as focus loop. In case of unstable status of actuator after jumping, the ON/OFF of tracking loop is controlled by TM7 switch of break circuit. After 10-track jumping, servo circuit gets out of the liner range and actuator's tracking becomes occasionally unstable. Hence unnecessary jumping with many tracking error should be prevented.
TE2 53 470K 57 TDFCT DFCTI 680K TG1 10K 66PF TM1 TGU 61 TG2 62 TG2 470K 20K 82K 110K
TRACKING PHASE COMPENSATION
TM4
680K TG1
49 TM3
TE-
10K
90K
50 +
TEO
TM7
6 FSET
Figure 16. Tracking servo block
M/M-97-P006 1997. 10. 17
23
PRELIMINARY
KB9223 / KB9223-L
2.3 Sled Servo Block
RF AMP & SERVO SIGNAL PROCESSOR
The moving of pick-up is controlled by tracking servo output through a low pass filter. The sled kick voltage is outputted for track jump operation.
TM6
43
SLO
TM7
PS + 4 X1 X2 X3 X4 0 0 1 1 3 0 1 0 1 TM2
44 42
SLSL+
Figure 17. Sled servo block
2.4 Spindle Servo Block The 20K resistor and 0.33uF capacitor form the 200Hz low pass filter, and the carrier component of spindle servo error signals is eliminated. In CLV-S mode, SMEF becomes "L" and pin 25 low pass filter fc lowers, strengthening the filter further. The characteristics of high frequency phase compensation in focus tracking servo and the characteristics of cut off frequency in CLV low pass filter are tested by FSET pin.
SMON 24
22K
22K
220K 15K 220K SMDP 23 20K 220K 15K 220K
+
100K
+
50K Double speed
46
SPDLO
45 SPDL-
25 SMEF
6 FSET
Figure 18. Spindle servo block
M/M-97-P006 1997. 10. 17
24
PRELIMINARY
KB9223 / KB9223-L
3.Digital Block 3.1 Description
RF AMP & SERVO SIGNAL PROCESSOR
Digital block is transferred serial data by micom and 8-bit serial data is converted to parallel data by serial to parallel register. This data is decoded by latch signal. The status output of focus servo,tracking servo,and sled servo system,etc is determined by each data. The auto-sequence function process 2~4 micom command by one auto-sequence command.
MDATA
D0
D1
D2
D3
D4
D5
D6
D7
twck twck MCK
tsu tsn
MLT
td twl
Figure 19. CPU serial interface timing chart
Table 4. CPU serial interface timing characteristics Item Clock Frequency Clock Pulse Width Hold Time Setup Time Delay Time Latch Pulse Width Symbol fck fwck tsu tn td twl Min 500 500 500 500 1000 Typ Max 1 Unit MHz ns ns ns ns ns
M/M-97-P006 1997. 10. 17
25
PRELIMINARY
KB9223 / KB9223-L
3.2 Micom Command Set Table 5. Servo control command set
Item Hexa D7 Focus Control Tracking Control Tracking Mode Select $0X $1X $2X $3X 0 0 0 0 Address D6 0 0 0 0 D5 0 0 1 1 D4 0 1 0 1 D3 FS4 Focus On Anti Shock
RF AMP & SERVO SIGNAL PROCESSOR
Data D2 FS3 Gain Down Brake On D1 FS2 Search On TG2 Gain Set D0 FS1 Search Up TG1 Gain Set
ISTA TOUT FZC A.S TZC STOP
Tracking Mode PS4 Focus Search+2 AS3 0.18ms PS3 Focus Search+2 AS2 0.09ms
Sled Mode PS2 Sled Kick+2 AS1 0.045ms PS1 Sled Kick+1 AS0 0.022ms
Auto Sequence R A M S E T Blind/ overflow Break Kick 2N jump move (M) Auto Adj. Speed
$4X
0
1
0
0
/ BUSY
$5X
0
1
0
1 0.36ms 0.18ms 5.80ms 32 64 0.09ms 0.09ms 16 32 0.045ms 0.045ms 8 16 -
Hi-Z
$6X
0
1
1
0
11.6ms 64
$7X
0
1
1
1
128
$8XX $FX
1 1
0 1
0 1
0 1
Offset,Balance,Gain,APC Control $F0:Normal Speed, $F3:Double Speed
M/M-97-P006 1997. 10. 17
26
PRELIMINARY
KB9223 / KB9223-L
3.2.1 Focus Control($0X)
RF AMP & SERVO SIGNAL PROCESSOR
This command consists of 8 bits data and expressed by two hexa $0X. D7 0 D6 0 D5 0 D4 0 D3 FS4 D2 FS3 D1 FS2 D0 FS1 ISTAT FZC
FS4,FS3,FS2,FS1:internal switch for focus control -Focus Search Operation(FS2,FS1) $02:FS2 switch become off and the value of servo output pin is as below. (10uA-5uA)*50k*(feedback Resistor/50k) $03:If FS1 switch is 1, the current supply is cut off and the discharge is performed. The waveform is as below and the time constant is determined by internal resistor 50K and external capacitor.
0V
Figure 20. Waveform at pin 3 when FS1 is switched from 0 to 1 The waveform of servo output pin according to FS1 and FS2 switches is as below.
$00
02
03
02
03
02
03
00
Figure 21. Focus search waveform at pin 48 by $02 and $03 FS4 is switch for on/off control of focus servo loop $00:Focus servo off $08:Focus servo on
M/M-97-P006 1997. 10. 17
27
PRELIMINARY
KB9223 / KB9223-L
3.2.2 Tracking Control($1X)
RF AMP & SERVO SIGNAL PROCESSOR
This command is used for tracking loop gain control, break circuit and anti-shock on/off control. D7 0 D6 0 D5 0 D4 1 D3 Anti shock on/off D2 Break circuit on/off D1 TG2 D0 TG1 ISTAT Anti shock
TG2 and TG1 are internal switch for tracking gain set. 3.2.3 Tracking mode($2X) This command is used for tracking and sled servo on/off and jump for searching track. D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0 ISTA T TZC
Tracking control
Sled control
D3 0 0 1 1 D2 0 1 0 1 Tracking mode Tracking servo off servo on Forward jump Reverse jump D1 0 0 1 1 D0 0 1 0 1 Sled mode Sled servo off servo on Forward kick Reverse kick
3.2.4 Peak value set($3X) This command is used for the peak value setting of focus search and sled kick . D0,D1:Sled kick D2,D3:Focus search peak value 3.2.5 Auto Sequencer command($4X) This command is used for reducing control time and replacing several command by one auto- sequence command. *Auto sequencer mode is performed from the first falling edge of WDCK clock after the falling of the latch pulse. *Auto sequencer does not carry out tracking gain up,brake,anti-shock and focus gain down. *Micom checks ISTAT pin(/BUSY) and sends to $40 command to reset preceding auto sequencer status
M/M-97-P006 1997. 10. 17
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PRELIMINARY
KB9223 / KB9223-L
RF AMP & SERVO SIGNAL PROCESSOR
Table 6. Auto sequence command Hexa Cancel Auto focus 1 Track jump 10 Track jump 2N track jump M track move $40 $47 $48 $49 $4A $4B $4C $4D $4E $4F AS3 0 0 1 1 1 1 1 1 1 1 AS2 0 1 0 0 0 0 1 1 1 1 AS1 0 1 0 0 1 1 0 0 1 1 AS0 0 1 0 1 0 1 0 1 0 1 Remark Reset Forward Reverse Forward Reverse Forward Reverse Forward Reverse
3.2.6 RAM Set($5X~$7X) The value of RAM set is somewhat different to the actual count and the initial value is like below Table 7. RAM set table Item Blind overflow, Brake Kick 2N ,M Track jump $67 $7E Initial value $55 actual count value Set value +4~5 WDCK clock Set value +3 WDCK clock Set value +5 WDCK clock Set value +3 WDCK clock
4.Auto Adjustment Command This command is used for auto control of offset,balance,gain adjustment and reference voltage setting. . This command is also in control of on/off and sub type of laser diode and test or set mode. 4.1 Tracking balance ($800~$81F) Item Tracking balance Hexa $800~$81F Data(5bits) D4~D0 initial value $81F ISTAT(pin31) BAL TRCNT(pin30) TRCNT
M/M-97-P006 1997. 10. 17
29
PRELIMINARY
KB9223 / KB9223-L
4.2 Tracking gain ($820~$83F) Item Tracking gain Hexa $820~$83F Data(5bits) D4~D0
RF AMP & SERVO SIGNAL PROCESSOR
initial value $820
ISTAT(pin31) GAIN
TRCNT(pin30) TGL
4.3 Tracking balance & gain window level setting Item window level setting Hexa $84X D3 gain D2 balance D1 0 D0 0 initial value $840
*The tracking balance and gain window level is set by D2,D3 data and the value has two kinds of window levels set 4.3.1 Tracking balance window level D2 data Tracking balance window level 0 -10~+15mV 1 -20~+20mV
4.3.2 Tracking gain window level D3 data Tracking gain window level 0 250~400mV 1 150~300mV
4.4 Focus loop offset adjustment start command($841,$842) This command is used for adjusting focus error bias and removing focus servo offset. This command is executed during laser diode off. Hexa command $841 $842 meaning Focus error bias adjustment start command Focus servo offset cancel adjustment start command
4.5 APC circuit operation and Interruption on/off setting condition($85X) This command is used for setting of laser diode on/off ,sub type(P_sub or N_sub) of laser diode and interruption countermeasure circuit on/off. Item APC & Interruption on/off condition Hexa $85X D3 LD on/off 0 : On 1 : Off D2 Sub-type 0:N_sub 1:P_sub D1 D0 initial value $858
Interruption ON/OFF and time setting
M/M-97-P006 1997. 10. 17
30
PRELIMINARY
KB9223 / KB9223-L
RF AMP & SERVO SIGNAL PROCESSOR
4.5.1 Time setting for Interruption countermeasure circuit on/off D1 0 0 1 1 D0 0 1 0 1 Meaning Countermeasure circuit on for all mirror signal Countermeasure circuit on up to 20KHz mirror signal Countermeasure circuit off Countermeasure circuit on up to 10KHz mirror signal
4.6 Focus servo offset reset command and set mode command (86X) This command is used for set and release before focus servo loop offset adjustment and mode change. Item Set mode & focus servo offset reset command Hexa $86X D3 0:offset release 1:offset reset D2 option (Pin41 output) 0:Defect 1:SSTOP D1 1 D0 1
(note1) The set mode command is sent by micom right after tracking gain is tuned. (note2) The ISTAT pin is outputted the internal status of $00 ~ $7X command. 4.7 Direct command(DIRC) and focus bias reset command($87X) This command is used for direct 1 track jump on/off setting and focus bias adjustment set and release Item DIRC & focus bias reset Hexa $87X D3 0:DIRC On 1:DIRC Off D2 0:reset 1:reset release D1 X D0 X
M/M-97-P006 1997. 10. 17
31
PRELIMINARY
KB9223 / KB9223-L
5.The Example of Adjustment Free Algorithm 5.1 Focus Error Bias & Servo Offset Cancel Adjustment
RF AMP & SERVO SIGNAL PROCESSOR
Focus_RF_Offset Adjustment [Command:841]
Increment Count 5bit Counter 17mV/Bit Tuning range : + 260mV no
ISTAT Check L--> H yes Finish [RF CNT value Latch]
Time Max 100msec
Focus_Servo_Offset Adjustment [Command:842]
Increment Count 4bit Counter 40mV/Bit tuning range : + 280mV no ISTAT Check L--> H yes Finish [Servo value Latch]
Time Max 100msec
Figure 22. Focus error bias & servo offset cancel adjustment flow chart
M/M-97-P006 1997. 10. 17
32
PRELIMINARY
KB9223 / KB9223-L
5.2 Tracking Balance Adjustment
RF AMP & SERVO SIGNAL PROCESSOR
Balance adjustment Range window setting + 20mv, + 15mv setting
$844
YES
ISTAT Check L--> H NO ISTAT Check L--> H NO
Micom Balance 5Bit adjustment Command Up
$800 ~ $81F
YES
Finish [RF CNT value Latch
Figure 23. Tracking balance adjustment flow chart 5.3 Tracking Gain Adjustment
Gain adjustment range setting Command
$848
ISTAT Check L--> H YES
NO
5 Bit Gain adjustment Command
$820 ~ $83F
Gain adjustment finish
TOC READ
Figure 24. Tracking gain adjustment flow chart
M/M-97-P006 1997. 10. 17
33
RF AMP & SERVO SIGNAL PROCESSOR
PRELIMINARY
to KA9258D
to KA9258D
to KA9258D
+
103p
222p
104p
120K 39K 0.47uF 333p 222p 100K
+
47K
VCC 104p 102p 1K
391p 47K 120K
104p
VC GNDVCC 1K 3.3uF
+
GND 10K
104p
15K
VCC
10K
100K 150K
683p
103p 56K
to KA9258D
10uF
from deck
FEBIAS
SPDLO
TDFCT
B C
65 PD1 66 PD2 67 F 68 E 69 PD 70 LD 71 VR 72 VCC
22K
SSTOP
FDFCT
SPDL-
DVDD
DVEE
ATSC
LPFT
TGU
TEO
FEO
SLO
TG2
TZC
FE1
FE2
TE1
TE2
SL+
TE-
FE-
SL-
A
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
FOK 40 MIRROR 39 RESET 38 MLT 37 MDATA 36 MCK 35 VSSA 34 EFM 33
to MOCOM
D VCC F
+
E 100uF
from MOCOM
22K
from MOCOM
from pick-up
from MOCOM
from MOCOM
102 33uF 33uF to pick-up
+ +
Figure 25. Application circuit
M/M-97-P006
34
73 RF74 RFO 75 IRF 76 EQO
103p
+
KB9223
ASY 32 0.47uF + ISTAT 31 TRCNT 30 LOCK 29 FGD 28 FS3 27 FLB 26
100K
4pF 472p
12K
to DSP
103p
to MOCOM
to MOCOM
from DSP
77 RFI 78 EQC 79 EI MUTEI WDCK GC2I GC2O 80 GND DCC2 DCC1 FRSH FSET MCP DCB
1uF
104p
104p
SMON
SMDP
GC1O
VREG
VDDA
VCCP
CH2O
CH1O
SMEF 25 VSSP CH2I GC1I CH1I ISET RRC
333p
1M 0.47uF
+
1
2
152p 103p
3
4
5
333p 4.7uF
+
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
150p 5.6K 331p 27K 103p 510K 27K 5.6K 5.6K 152p
+ +
331p 5.6K 5.6K
+
150p 4.7uF
+
KB9223 / KB9223-L
180K
8.2K
APPLICATION CIRCUIT
27K 5.6K 152p
VCC(POST)
4.7uF from DAC CH2
4.7uF
+
GND (POST)
from DSP(SMDP)
from DSP(SMON)
VCC
from DSP(SMSD)
from DAC CH1
from MICOM
CH1 out
CH2 out
from DSP
from DSP(SMEF)
27K
1997. 10. 17

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